Accordingly, apparatuses called testers are used for checking the operation of electronic circuits, and integrated circuits often comprise structures which are not used during the normal operation but the only aim of which is to facilitate the checking of the good operation of the circuit.
Generally, testers are apparatus used on the one hand by the manufacturers of integrated circuits or complex electronic circuits, on the other hand, by users who test again each of the circuits they have acquired while, often, the manufacturer makes thorough checking only on a sampling of the circuits he manufactures and validates a batch as soon as a given percentage of the circuits in the batch appears to be fully good.
In any case, it is desirable that a tester presents the following features:
high speed and precision; indeed, a great number of tests are to be carried out on complex components and it is desirable that the elementary time duration used by each of the tests is as short as possible;
easiness of programmation and simplicity of use;
modular design for permitting that a same tester be able to test different circuits while minimizing the changes to the tester.
In the present application, only the testers permitting check of the operation of the whole set of pins of an electronic circuit will be considered and not the single-pin or single-way testers which exhibit modularity advantages but cost drawbacks, because, if it is desired to test a plurality of pins one has to duplicate a great number of circuits existing on each such tester, such as the test vector processor, the delay generation circuits, the various analog references, etc. Due to those duplications, those single-pin testers also exhibit the drawback that the test conditions are not reproducible from one way as testing to another. Additionally, in those structures, the test vectors are arranged bit by bit in the memories of the different ways and are accordingly difficult to be accessed by the operator.
As regards the operations to be carried out, a tester usually implements successively three types of controls.
First, a likeliness control, that is a rough control wherein it is simply checked whether the various supplies and the various input/output ports are not shortened or open.
Second, a parametric control wherein it is checked at each input/output whether the impedance is within an acceptable range for the various signals. In those two first controls, analog values are measured and set time values are to be taken into account. Each individual test has typically a time duration of some milliseconds. On an integrated circuit comprising 256 pins, about 500 tests will be carried out for the parametric control.
Thirdly, a functional control wherein the suitable operation of the circuit is checked. In this purpose, a series of signals, called test vectors, shaped as regards their duration and their amplitude are sent on one or a plurality of circuit pins, and it is checked at one or a plurality of other pins if the response received signals correspond effectively to the desired function of the circuit. During the functional control, the speed of the logic circuit is also checked. Typically, an elementary functional test has a duration of about 100 ns and 4,000 tests are implemented for an integrated circuit comprising 256 pins.
An example of a known test machine is schematically shown in FIG. 1. This machine comprises a central processing unit 10 connected on the one hand to external elements such as a terminal 11, a printer 12, and a port 13 for establishing a link with other apparatus, for example a communication link towards an host computer. On the other hand, the central processing unit 10 is connected to a bus 14 for transmitting and receiving data towards and from various elements of the tester.
The circuit to be tested is connected to the tester through a plug board, not shown, and a load board 15, the input/output connections of which correspond to the number of pins of the element to be tested. Each of those connections is connected to a specific card, called electronic pin, 16, only one of which is shown in FIG. 1 and which constitute, in fact, a set of boards, geometrically arranged generally as a ring. Those cards 16 comprise, on the one hand, a bidirectional link towards a test vector memory 17 and a specific link towards a terminal of the load board 15 and, on the other hand, access to common circuits for providing reference voltages, 19, and time delays, 19', to the general bus 14. Each electronic pin 16 comprises amplitude and time shaping circuits for adjusting the signals received from memory 17 to the references provided by circuits 19 and 19'. The load board 15 comprises buffer impedances and switches for connecting the pins to be tested either to an electronic pin or to a central measuring unit 18 which applies currents and measures voltages or conversely.
Each of the elements 15, 16, 17, 18, 19, 19' has to be programmed for insuring a satisfactory operation and is connected to the common bus 14; each of those elements, or each of the sub-sets constituting each of those elements, has a specific address permitting recognition as the signals from the bus addressed thereto and, conversely, can send back onto the bus characteristic signals that are detected by the CPU 10.
This description of a prior art tester is very schematic; its main aim is to show the whole architecture of a conventional tester based on a central CPU and a common interconnection bus together with units that are parallel connected with different addresses and each of which carries out one of the elementary functions of the tester.
In such a structure, the operation of the units 15, 16, 18, 19, 19' and the operations to be carried out onto those units are unavoidably relatively slow, for example in the range of some milliseconds or some tenths of millisecond. On the contrary, the memory 17 that contains the test vectors to be sent towards the circuit to be tested and the vectors received therefrom, has to be read and written at a very fast rate, usually in the range of some tenths of nanoseconds. In fact, the read/write speed of the memory has to correspond to the maximal speeds for which the circuit to be tested has been designed, for checking its high frequency operation. Accordingly, the CPU 10 has to manage in a very fast way the test vector memory 17 through the bus 14. This memory 17 is a large scale memory, containing for example some megabytes. Accordingly, in the prior art testers, various sophisticated means have been used for maximizing this management speed but this causes very complex technical solutions because the bus 14 is heavily loaded due to the fact of its great number of connections with a plurality of units and accordingly its transmission speed is a priori limited.
Additionally, the fact of providing a central circuit 19' transmitting to various boards (electronic pins) time signals for fixing phase references causes those phase references to unavoidably include systematic errors, different for the different pins, due to the time delays caused by the wire lengths that cannot be neglected in such complex circuits.
Thus, an object of the invention is to provide a tester, the general architecture of which permits an increase of the management speed of the test vector memory.
Another object of the invention is to provide a tester wherein the link between the tested circuit and the logical portions of the tester is improved for permitting a highest modularity.
A further object of the instant invention is to provide a tester permitting to obtain very precise time phase references.